FIG. 1 is a circuit diagram illustrating a configuration of a conventional discharge tube lighting apparatus with no synchronization signal being inputted thereto. FIG. 2 is a timing chart illustrating signals at various parts of the conventional discharge tube lighting apparatus with no synchronization signal being input thereto. In the discharge tube lighting apparatus as illustrated in FIG. 1, connected between a DC power source Vin and the ground is a first series circuit having a high-side p-type MOSFET Qp1 (referred to as p-type FET Qp1) and a low-side n-type MOSFET Qn1 (referred to as n-type FET Qn1). Between a connection point of the p-type FETQp1 and n-type FET Qn1 and the ground GND, there is connected a series circuit having a capacitor C3 and a primary winding P of a transformer T. Both ends of a secondary winding S of the transformer T are connected to a series circuit having a reactor Lr and a capacitor C4
A source of the p-type FET Qp1 receives the DC power source Vin and a gate of the p-type FET Qp1 is connected to a terminal DRV1 of a controller IC 1. A gate of the n-type FET Qn1 is connected to a terminal DRV2 of the controller IC 1.
The controller IC 1 has a start circuit 10, a constant current determination circuit 11, an oscillator 12, a frequency divider 13, an error amplifier 15, a PWM comparator 16, a NAND gate 17a, an AND gate 17b, and drivers 18a and 18b. The constant current determination circuit 11 is connected through a terminal RF to an end of a constant current determination resistor R1. The oscillator 12 is connected through a terminal CF to an end of a capacitor C1.
The start circuit 10 receives source power from the DC power source Vin to generate a predetermined voltage REG and supply the same to various internal parts. The constant current determination circuit 11 passes a constant current that is optionally set by the constant current determination resistor R1. According to the constant current from the constant current determination circuit 11, the oscillator 12 charges and discharges the capacitor C1, to generate a sawtooth oscillating waveform illustrated in FIG. 2 (illustrated in FIG. 2 is a charge/discharge voltage of the capacitor C1 at the terminal CF), and according to the sawtooth oscillating waveform, generates a clock CK. The clock CK has, as illustrated in FIG. 2, a pulse voltage waveform that is synchronized with the sawtooth oscillating waveform at the terminal CF so that it becomes high level during a rise period of the sawtooth oscillating waveform and low level during a fall period of the same. The clock CK is sent to the frequency divider 13.
An end of the secondary winding S of the transformer T is connected through the reactor Lr to an electrode of a discharge tube 3, the other electrode of the discharge tube 3 being connected to a tube current detection circuit 5. The tube current detection circuit 5 has diodes D1 and D2 and resistors R3 and R4, to detect a current passing through the discharge tube 3 and output a voltage proportional to the detected current to an inverting terminal (as depicted by “−”) of the error amplifier 15 through a feedback terminal FB of the controller IC 1.
The error amplifier 15 amplifiers an error voltage FBOUT between the voltage from the tube current detection circuit 5 input to the inverting terminal and a reference voltage E1 input to a non-inverting terminal (as depicted by “+”) and sends the error voltage FBOUT to a non-inverting terminal (as depicted by “+”) of the PWM comparator 16. The PWM comparator 16 generates a pulse signal that is high level if the error voltage FBOUT from the error amplifier 15 inputted to the non-inverting terminal is equal to or higher than the sawtooth waveform voltage from the terminal CF input to a non-inverting terminal (as depicted by “+”) and low level if the error voltage FBOUT is lower than the sawtooth waveform voltage. The pulse signal is outputted to the NAND gate 17a and AND gate 17b. 
The frequency divider 13 divides the frequency of the pulse signal from the oscillator 12 and provides the NAND gate 17a with a frequency-divided pulse signal Q and the AND gate 17b with a pulse signal (having a predetermined dead time with respect to the frequency-divided pulse signal Q) formed by inverting the frequency-divided pulse signal Q. The NAND gate 17a operates the NAND function of the frequency-divided pulse signal from the frequency divider 13 and the signal from the PWM comparator 16 and outputs a drive signal through the driver 18a and terminal DRV1 to the p-type FET Qp1. The AND gate 17b operates the AND function of the inverted frequency-divided pulse signal from the frequency divider 13 and the signal from the PWM comparator 16 and outputs a drive signal through the driver 18b and terminal DRV2 to the n-type FET Qn1.
During from time t1 to t2, for example, the output from the PWM comparator 16 is high level, the output from the frequency divider 13 is high level, and the output of the NAND gate 17a is low level. As a result, the terminal DRV1 provides a low-level output to turn on the p-type FET Qp1. From time t4 to t5, the output from the PWM comparator 16 is high level, the inverted output from the frequency divider 13 is high level, and the output from the AND gate 17b is high level. As a result, the terminal DRV2 provides a high-level outputted to turn on the n-type FET Qn1.
Namely, the drive signals are formed by synthesis with the outputs from the frequency divider 13 and are alternately sent to the terminals DRV1 and DRV2 in synchronization with the clock CK with a fall period of the sawtooth oscillating waveform serving as a dead time. With the above-mentioned operation, the controller IC 1 alternately turns on/off the p-type FET Qp1 and n-type FET Qn1 at the frequency of the sawtooth oscillating waveform. As results, power is supplied to the discharge tube 3 and a current passing through the discharge tube 3 is controlled at a predetermined value.
The oscillation frequency of the oscillator 12 arranged in the discharge tube lighting apparatus illustrated in FIG. 1 is generally determined by the resistor R1 and capacitor C1. However, due to variations among the employed parts (the resistor and capacitor), the oscillation frequency may interfere with a low oscillation frequency of burst dimming and the oscillation frequency of an SMPS arranged before the discharge tube lighting apparatus, to cause screen flickering that is critical for a display device.
To cope with this, there is a method that inputs an external synchronization pulse voltage signal to the discharge tube lighting apparatus, to synchronize and regulate the oscillation frequency of the oscillator 12 with respect to the external synchronization pulse voltage signal. In this case, the lighting frequency of a discharge tube is synchronized with the frequency of the external synchronization pulse voltage signal, or ½ of the frequency of the external synchronization pulse voltage signal. For example, to synchronize the lighting frequency of a discharge tube with a synchronization pulse voltage signal from a microcomputer, a synchronization circuit illustrated in FIG. 3 is added.
The synchronization circuit illustrated in FIG. 3 has a one-shot circuit 2 to generate a one-shot pulse at a rise time of an external synchronization pulse voltage signal TRI, a diode D3 connected to an output of the one-shot circuit 2 and an end of a capacitor C1, and a Zener diode ZD1 connected to both ends of the capacitor C1. This synchronization circuit provides the capacitor C1 with the synchronization pulse voltage signal TRI whose frequency is higher than the frequency of a sawtooth oscillating waveform CF of the capacitor C1, as illustrated in FIG. 4, to synchronize the sawtooth oscillating waveform CF of the capacitor C1 with the frequency of the synchronization pulse voltage signal TRI, thereby synchronizing the lighting frequency of the discharge tube 3 with ½ of the frequency of the synchronization pulse voltage signal TRI.
A known related art is, for example, U.S. Pat. No. 5,615,093. According to this document, a secondary winding of a transformer is connected to a load. A primary winding of the transformer is provided with a semiconductor switch circuit. Each switch of the semiconductor switch circuit is PWM-controlled to conduct constant-current control. If a state of instructing the stoppage of an operation/stop signal is established, a power source to a control circuit part is disconnected to set a standby state. At the same time, switch drive signals that turn on the switches in the semiconductor switch circuit are turned off, to prevent the occurrence of an excessive current at the time of shifting to the standby state.